NAND flash based SSDs have been growing in capacity faster than any other type of semiconductor memories. This has been propelled by aggressive semiconductor die shrink and by increasing the number of bits per cell, as well as stacking layers of NAND vertically. With die sizes as small as 7nm, and 4 bits per cell, further growth is constrained by physical limitations. Modern SSDs use 2 or 4 or 8 charge levels in each flash cell to represent 1, 2, or 3 bits respectively. These technologies are referred to as Single-Level Cell (SLC), Multi-Level Cell (MLC), and Triple-Level Cell (TLC). With Quad-Level Cell (QLC) SSDs, there are 16 distinct levels of charge in each cell to represent 4 bits. With just dozens of electrons per cell, distinguishing between 16 charge levels becomes harder, both to read and write data. With smaller tolerances at nanometer scale, these SSDs are prone to charge leaks, causing bit errors. Thus, QLC SSDs face increased bit errors as electrons can leak or tunnel through the barriers, and in rare cases, even across transistors. These SSDs will wear out at a much faster rate, down to about a thousand Program-Erase (P/E) cycles, a third of TLC flash, and a hundredth of SLC flash. This causes significant limitations to the use of QLC flash at enterprise, scientific and industrial scale. The Mean Time To Failure (MTTF) for an enterprise QLC SSD is 0.66× of an equivalent TLC SSD. However, if some of these limitations are addressed, QLC provides a low-cost, high-throughput low-latency flash based storage, which could improve the efficiency of archival systems and open up new possibilities in storage architectures. We explore the issues that arise from increased error rates and increased failures, and propose solutions for them which will make QLC SSDs viable for large scale storage. We look at new tiering strategies for storage stacks, explore zoned storage strategies and work on new coding techniques to address the challenges faced by QLC SSDs.